1. Field of the Invention
The invention relates to computer memory systems and, more particularly, to the refresh of DRAM storage elements in such memories.
2. History of the Prior Art
Data processing systems for computers use memory to store information. More specifically, the data processor of a computer stores individual units of information consisting of a specific number of bits representing binary digits at specific locations within a memory unit. The locations within the memory where data bits are stored, are specified by addresses. Each address consists of a specific number of bits and the total number of bits available for address information defines the total number of memory locations that can be addressed within the computer. The total number of addressable memory locations, in turn, provides a limit to the amount of information that can be stored and accessed by the data processor. This limitation in memory limits the capability of the data processor in performing its data processing functions.
Depending on their access characteristics, computer memory units may be categorized in either of two types of memory configurations. One type of memory unit is referred to as the read only memory (or "ROM") type of memory. In general, ROMs are characterized by the permanent storage of memory at selected locations. A random access memory (or "RAM"), on the other hand, is generally characterized by the ability to both write information into and read information out of the memory at any location and in any desired sequence.
A typical RAM consists of a plurality of memory cells, an address decoder, read/write control circuitry and a memory output register. While there are many variations in the structure of and interconnection between the basic elements of RAMs which are utilized to separate different RAM designs into numerous classifications, RAMs may be separated into two distinct types based on the structure of the memory cells used in the memory unit--the "static" RAM (or "SRAM") and the "dynamic" RAM (or "DRAM"). In the SRAM, each memory cell consists of a flip-flop circuit comprised of 4-6 transistors or other semiconductor devices and each memory cell has, therefore, two stable states. As long as power is supplied to the memory cells, the information stored in the cells will be maintained.
In contrast, each memory cell of a DRAM includes a microscopic "storage" capacitor consisting of two conductive layers separated by an insulator. The memory cell of a DRAM stores a single bit of information in the microscopic capacitor as the presence or absence of an electric charge in that capacitor. A charged capacitor generally represents a "1" and a discharged capacitor generally represents a "0". Usually, a single transistor is used to control charging the storage capacitor.
Since the electric charge stored in the storage capacitor of a memory cell will gradually leak away, the stored information must be periodically rewritten into the cell before the charge completely leaks out. This periodic rewriting of the information previously stored in the memory cell is called "refreshing" the memory. The frequency at which a memory cell must be refreshed varies depending on the rate of leakage in the control transistor. In a typical DRAM, each memory cell must be refreshed every two, four or eight milliseconds.
Although the refreshing operation requires additional circuitry to coordinate the procedure, the DRAM is often used due to certain advantages over the SRAM. For example, because the DRAM requires only a single control transistor while the SRAM requires 4 to 6 transistors, the DRAM occupies a much smaller area on the silicon substrate than the SRAM and is less expensive to manufacture. Furthermore, the DRAM consumes less power than a SRAM. Thus, DRAMS are particularly attractive in most microcomputer systems where space and power consumption are at a premium.
In a memory unit which is comprised of DRAMs, both memory access (i.e. writing to or reading from a memory cell) and refresh operations are controlled by a combination of a pair of signals called a row address strobe (or "RAS") signal and a column address strobe (or "CAS") signal, respectively. During a memory access operation, the RAS and CAS signals are used to select the particular memory cell to be accessed. Some DRAMs also require manipulation of both the RAS and CAS signals to perform a refresh cycle. Other DRAMs may be refreshed by activating only the RAS signal.
During a refresh operation which requires both the RAS and the CAS signals to refresh the memory unit having DRAMs, information is read out of any number of memory cells and then rewritten back into the cells where the information will remain for the maximum time limit between refresh cycles. Typically, the circuitry corresponding to such conventional refresh operations is arranged so that a refresh cycle occurs after each memory access such that an entire row of memory cells will be refreshed at the same time. As a result, accessing any cell in a particular row causes the entire row to be refreshed. Other memory units which include DRAMs require only a RAS signal to perform a refresh operation. In these devices, when a row address is presented to the DRAM, the RAS signal goes active, thereby refreshing all locations which have the same row address. To completely refresh this type of DRAM memory unit, therefore, it is required to sequentially cycle through all of the row addresses within the maximum time limit.
When a computer system is provided with large amounts of memory, the need to constantly refresh DRAMs can create numerous problems. For example, many memory units now include four megabit DRAMs having 1024K row addresses. The computer system which is the subject of the present application, employs a memory unit which may include up to eight double-sided, single in-line memory modules (or "SIMMs") where each side of a SIMM will store 32 bits of a 64 bit data word at the 1024K address locations of a 4 Megabit DRAM. Still other configurations of the memory unit which include even larger amounts of memory are also contemplated. Because of the large size of the memory unit provided in the computer system which incorporates the present invention therein, any attempt to simultaneously refresh all of the DRAM SIMMS would require a substantial amount of power to simultaneously provide a RAS signal to every row of every memory bank in the memory unit. Since there is a plurality of memory banks, the refresh power requirement for refreshing all memory banks simultaneously would generate a large power surge, resulting in possible electromagnetic interference problems, as well as require an excessive amount of power service.
For these reasons, large memory systems which utilize DRAMs have traditionally included associated circuitry which staggers the refresh signals to the different banks in the memory system. In such a configuration, the staggered refresh circuit would generate a row address to all of the memory banks and generate a RAS pulse to instruct the DRAMs to latch the row address to each of the banks in turn.
Various staggered memory refresh systems for DRAMs are known. For example, U.S. Pat. No. 4,601,018 to Baum et al. discloses a refresh system where a series of memory banks are refreshed at different times. In Baum et al., the memory refresh circuit is connected to a display circuit whereby outputs of the display circuit determine when memory refresh is required and which banks of memory are to be refreshed. The inputs to the memory refresh timing circuitry determine the appropriate time intervals to refresh selected memory banks. While Baum et al. provides for timing requirement modification, Baum et al. does not provide any circuitry for altering the sequence of refresh timing based on the memory configuration.
Such prior systems do not provide sufficient flexibility to maximize the efficiency of the memory refresh sequence for the memory unit. Depending on the particular configuration of a computer system, any number of memory slots included in a memory unit may have a memory bank installed therein. For example, a system incorporates a memory unit having eight slots which are each capable of having a memory bank installed therein, and if only four of the slots actually have memory banks installed, a refresh cycle which sequentially issues a memory refresh signal to each slot would be inefficient. It would be preferable that the memory refresh sequence would issue refresh signals only to those slots in which memory banks had been installed. Not only would such a capability improve the efficiency of the refresh sequence, it would improve access to the memory unit as well.
In addition, many memory refresh systems do not permit data to be written to or read from the memory during refresh operations. Such restrictions in prior systems result in an unnecessarily long refresh sequence which seriously restricts the bandwidth within which the processor can access the memory unit. Thus, the primary purpose of the memory unit, i.e., the rapid storage and retrieval of large amounts of data is degraded.
A flexible memory refresh sequence would also be advantageous when the memory unit of a computer is upgraded or otherwise modified after the initial configuration of the computer system. For example, a memory unit consisting of a single memory card may initially have memory banks installed in only four out of the eight available slots typically provided on a memory card. Increased memory requirements in the computer system may later require that additional memory banks be installed. If the memory refresh sequence is designed based upon the initial memory configuration, changes such as memory upgrades would require resequencing of the refresh signals in order to keep them operating at optimum efficiency. To reduce the time required to modify the refresh sequence, it would be desirable to provide a refresh sequence controller which would maximize the ease with which the refresh sequence can be modified so that efficiency of the refresh sequence is maximized for any particular memory unit configuration.
Finally, when prior art memory units were of sufficient memory capacity that plural refresh sequence controllers were required, the sequence controllers were typically tied directly together. As a result, the installation of an additional memory card or other increase in memory size in a prior art memory would often require an additional sequence controller and necessitate extensive modification to the existing sequence controllers in order to interconnect them. If stand-alone refresh sequence controllers were provided, however, a computer system could be more readily modified to accommodate expansion of the memory unit by requiring only the installation of an additional refresh sequence controller.